@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN225 |Writing default property annotation file D:\DSP reference guide\DSP Reference Guide\Ref. Guide Design Examples\Liberov11.3\VHDL\Filters\Semi- Parallel FIR filters\Two Multiplier 8-Tap FIR\TwoMult_8Tap_FIR\synthesis\TwoMult_8_tap_FIR.sap.
